An approach to saving power in integrated electronic devices involves sampling a reference voltage. This reference voltage is usually generated by a band gap reference generator on a capacitor. While the reference voltage is stored on the sampling capacitor, the reference generator circuit can be switched off or put in a power down mode to reduce static power consumption. This reduces the average supply current of the reference generator and leads to lower power consumption.
The voltage on the sampling capacitor decreases over time primarily by parasitic leakage currents. Thus there must be a refresh mechanism for the sampled voltage. This refresh mechanism ensures that the reference voltage stays within a certain range. A prior art solution compares the voltage sampled on the sampling capacitor to a specific reference voltage. When the voltage on the sampling capacitor is equal to the reference voltage, a comparator triggers a refresh of the voltage on the sampling capacitor. The circuitry needed to implement this control loop requires a comparator, an additional reference voltage generator which cannot be switched off and further biasing circuitry. Accordingly, the power consumption and the chip area needed to implement the circuitry is large. This counteracts the desired power savings. Another prior art approach uses a fixed periodic refresh cycle selected for the worst case. This fixed periodic refresh cycle is carried out as if the highest leakage current were present irrespective of the sampling capacitor's actual leakage current. Accordingly, both the refresh rate and the power consumption are unnecessarily high.